1. Field of the Invention
The present invention relates to an optical logic device which performs a logic operation on a plurality of input light signals, and particularly, to an optical logic device enabled to perform an optical operation on electric signals without performing time base adjustment on the electric signals after input light signals are converted into the electric signals.
2. Description of the Related Art
In optical communication systems, measuring apparatuses for optical communication, optical computers, and so on, logic operations, such as AND-operations, and OR-operations, are performed on multiple input light signals. Hitherto, a photoelectric conversion portion is provided corresponding to each of the input light signals. Then, these photoelectric conversion portions convert the input light signals into electric signals. The logic operations are formed on the converted electric signals (See, for example, the following document (1), that is, JP-A-10-50870.).
FIG. 6 is a diagram illustrating the configuration of a conventional circuit for performing logic operations. As illustrated in FIG. 6, a light signal delay portion 10a, to which an input light signal S1 is inputted, delays the input light signal S1 by a predetermined time and outputs the delayed signal S1. A photoelectric conversion portion 20a, to which the input light signal S1 outputted from the light signal delay portion 10a is inputted, outputs an electric signal, which has a voltage level corresponding to the light intensity of this input light signal S1.
A light signal delay portion 10b, to which an input light signal S2 is inputted, delays the input light signal S2 by a predetermined time, and outputs the delayed signal S2. A photoelectric conversion portion 20b, to which the input light signal S2 outputted from the light signal delay portion 10b is inputted, outputs an electric signal, which has a voltage level corresponding to the light intensity of this input light signal S2. Incidentally, a delay optical fiber and a quartz optical waveguide, which have desired lengths, are used as the light signal delay portions 10a and 10b. 
A logic synthesis processing circuit 30 has an electric signal delay portion 31, and receives electric signals, which are inputted from the photoelectric conversion portion 20a and a photoelectric conversion portion 20b. Then, the logic synthesis processing circuit 30 performs logic operations (for example, AND-operations and OR-operations) and outputs results of the operations.
An operation of such a device is described hereinbelow.
The input light signals S1 and S2 are respectively inputted to the light signal delay portions 10a and 10b, respectively. Usually, the input light signals S1 and s2 are not simultaneously inputted to the light signal delay portions 10a and 10b, respectively, so that the deviation between the time bases of signals representing bits, on which a logic operation is performed, is caused. The causes of the deviation between the time bases are, for example, the difference in the distance or the material of transmission paths. The light signal delay portions 10a and 10b provide predetermined time delay amounts to the input light signals S1 and S2, respectively, to perform time base adjustment. Thus, the input light signals S1 and S2, which are timed, are outputted to the photoelectric conversion portions 20a and 20b. 
Then, the photoelectric conversion portions 20a and 20b convert the input light signals S1 and S2 into electric signals and output the electric signals to the logic synthesis processing circuit 30. Subsequently, the electric signal delay portion 31 of the logic synthesis processing circuit 30 delays at least one of the converted electric signals by a predetermined time in such a way as to include a signal delay amount generated in an electric circuit in the logic synthesis processing circuit 30, so that the electric signals are timed. Further, logic operations are performed at an AND-circuit (not shown) and an OR-circuit (not shown) of the logic synthesis processing circuit 30, which then outputs results of the operations.
Next, the photoelectric conversion portions 20a and 20b are concretely described. FIG. 7 is a diagram illustrating an example of the configuration of each of the photoelectric conversion portions 20a and 20b. In this figure, components, which are the same as those shown in FIG. 6, are designates by the same reference characters as used for designating those in FIG. 6. Thus, the description thereof is omitted herein. As shown in FIG. 7, a resistor Rb is connected to a constant-voltage power supply Vcc at a terminal thereof. A capacitor Cb is connected to the other terminal of the resistor Rb at a terminal thereof, and also connected to the ground GND, which provides common electric potential, at the other terminal thereof. Further, the resistor Rb and the capacitor Cb constitute a bias circuit BC.
A photodiode PD is a photoreceiver and connected to the other terminal of the resistor Rb at a cathode thereof. Input light signals S1 and S2 are inputted to the photodiode PD (FIG. 7 illustrates an example in which the input light signal S1 is inputted thereto). A resistor RL is connected to an anode of the photodiode PD at a terminal thereof, and also connected to the ground GND at the other terminal thereof. An output terminal Vout is connected to the anode of the photodiode PD.
Incidentally, the resistor Rb of the bias circuit BC is a protective resistor for preventing the constant-voltage power supply from applying an overvoltage to the photodiode PD. Further, the capacitor Cb reduces noises originated from the constant-voltage power supply Vcc. Therefore, it is advisable to provide the bias circuit BC in the circuit, as need arises.
An operation of such a circuit is described hereinbelow.
When an input light signal S1 is inputted to the photodiode PD, the photodiode PD outputs a photocurrent corresponding to the light intensity thereof. Then, the photocurrent flows to the ground GND through the resistor RL. Thus, an electric signal having a voltage level corresponding to the light intensity of the input light signal S1 is outputted to the output terminal Vout.
Further, another example of each of the photoelectric conversion portions 20a and 20b is described hereinbelow. FIG. 8 is a diagram illustrating another example of the configuration of each of the photoelectric conversion portions 20a and 20b. Additionally, FIG. 8 shows what is called a balanced photoreceiver (See, for instance, the following document (2)). Incidentally, components, which are the same as those shown in FIG. 7, are designated by the same reference characters used for designating such components in FIG. 7. Thus, the description of such components is omitted herein.
As shown in FIG. 8, a bias voltage is applied to the photodiode by a bias-T BT1, which is connected to the constant-voltage power supply Vcc at a terminal thereof. The photodiode PD1 is connected to the other terminal of the bias-T BT1 at the cathode thereof. The photodiode PD2 is connected to the anode of the photodiode PD1 at a cathode thereof. That is, the photodiodes PD1 and PD2 are series-connected to each other. Incidentally, preferably, photodiodes having the same characteristics (for example, a dark current characteristic, a response speed characteristic, and a conversion efficiency characteristic) are used as the photodiodes PD1 and PD2. The bias-T BT2 is connected to the anode of the photodiode PD2 at a terminal thereof, and also connected to a constant-voltage Vee (Vcc>GND>Vee).
A capacitor C1 is connected to the other terminal of the bias-T BT1 at a terminal thereof and also connected to the ground GND at the other terminal thereof. Another capacitor C2 is connected to a terminal of the bias-T BT2 at a terminal thereof and also connected to the ground GND at the other terminal thereof. A resistor RL1 is connected to the other terminal of the capacitor C1 at a terminal thereof and also connected to the anode of the photodiode PD1 at the other terminal thereof. Another resistor RL2 is connected to the other terminal of the resistor RL1 at a terminal thereof and also connected to the other terminal of the capacitor C2 at the other terminal thereof. An output terminal Vout is connected to the other terminal of the resistor RL1. An optical coupler CP branches the input light signal S1 into two signals and outputs these two signals to the photodiodes PD1 and PD2, respectively.
An operation of such a circuit is described hereinbelow.
The input light signal S1 is branched by the optical coupler CP in two signals, which are inputted to the photodiodes PD1 and PD2, respectively. Incidentally, the optical coupler CP branches the input light signal S1 into two signals that have equal light intensity. Therefore, photocurrents outputted by the photodiodes PD1 and PD2 become differential signal photocurrents that are completely dependent of and reversed to each other. Furthermore, electric signals obtained by converting these photocurrents into voltages are outputted from the output terminal Vout.
The following documents are related to as referred to as related art.
(1) JP-A-10-50870 (Paragraph No. 0002).
(2) Heinz-Gunter Bach: “InP-Based High-Speed Photoreceivers for Optical Fiber Communications”, 11th ECIO' 03 1.-4, USA, IEEE, Vol. 2, paper ThB3, pp. 123-134.
Thus, the photoelectric conversion portions 20a and 20b shown in FIGS. 7 and 8 convert the light signals, whose time bases are adjusted, into the electric signals, respectively. The logic synthesis processing circuit 30 performs logic operations on the electric signals converted separately from each other.
The transmission rate of the input light signals S1 and S2 in the optical waveguide or the optical fiber, in which the input light signals S1 and S2 are transmitted, is almost constant. Thus, the timing adjustment of the input light signals S1 and S2 can easily be performed by the light signal delay portions 10a and 10b. Further, change of the transmission rate can easily be achieved only by changing the length of the optical waveguide or the optical fiber.
However, the logic synthesis processing circuit 30 performs logic operations by using the electric signals respectively outputted from the plurality of photoelectric conversion circuits 20a and 20b. Thus, it is necessary to set an amount of delay, which is generated by the electric signal delay portion 31, by taking a delay amount of the electric signal, which is generated in the electric signal provided in the logic synthetic processing circuit 30, into account. Furthermore, because the amount of the generated delay varies with the kinds (AND-operation, OR-operation, and so forth) of the logic operations, there is need for setting the delay amounts generated by the electric signal delay portion 31, which are respectively associated with the kinds of the logic operations. Furthermore, even among devices of the same kind (for instance, transistors), there are differences in the delay amount. Thus, the setting of the delay amounts generated by the electric signal delay portion 31 is very difficult.
Furthermore, because the duration of each bit varies according to the transmission rate (expressed as, a bit rate), the delay amount introduced by the electric signal delay portion 31 should be set again when the transmission rate of the input light signals S1 and S2 are changed. However, it is very difficult to set again the delay amount. Thus, the logic operations are substantially performed on the basis of electric signal processing associated only with a fixed transmission rate.
Additionally, the electric signal delay portion 31 processing the electric signals can adjust the delay amount even in the case where the bit rate of the electric signal is 1 Gbps or so. However, in the case of a high bit rate (for example, 10 Gbps to 40 Gbps), it is very difficult for the electric signal delay portion 31 to perform the delay amount adjustment itself.